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INTEGRATED CIRCUITS
DATA SHEET
PCA84C646; PCA84C846 Microcontrollers for TV tuning control and OSD applications
Preliminary specification Supersedes data of June 1994 File under Integrated Circuits, IC14 1995 Jun 15
Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
CONTENTS 1 1.1 1.2 2 3 4 5 5.1 5.2 6 6.1 6.2 7 7.1 7.2 8 9 9.1 9.2 9.3 9.4 10 10.1 10.2 10.3 10.4 11 11.1 FEATURES PCF84CXXXA kernel VST and OSD derivative GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING INFORMATION Pinning Pin description RESET Reset trip level Reset status ANALOG CONTROL 6 and 7-bit PWM outputs (PWM00 to PWM07) VST control 14-bit PWM DAC AFC INPUT OSD (ON SCREEN DISPLAY) FUNCTION Features Horizontal display position control Vertical display position control Clock generator DISPLAY RAM ORGANIZATION Description of display RAM codes Loading character data into display RAM Writing character data to display RAM Default value of the display character CHARACTER ROM Character ROM organization 12 12.1 12.2 12.3 12.4 12.5 12.6 12.7 13 14 14.1 14.2 15 16 17 18 19 20 21 22 23 24 25 26 27 28
PCA84C646; PCA84C846
OSD CONTROL REGISTERS Derivative Register 22 (CON1) Derivative Register 23 (CON2) Derivative Register 33 (CON3) Derivative Register 34 (CON4) Derivative Register 35 (VPOS) Derivative Register 36 (HPOS) Derivative Register 37 (BCC) COMBINATION OF TWO OR MORE FONT CELLS TO FORM A NEW FONT OSD CLOCK IN DIFFERENT TV STANDARDS Maximum number of characters per row Maximum number of rows per frame T3: 8-BIT COUNTER I2C-BUS MASTER SLAVE TRANSCEIVER DERIVATIVE REGISTERS INPUT/OUTPUT OPTION LISTS LIMITING VALUES DC CHARACTERISTICS AC CHARACTERISTICS AFC CHARACTERISTICS PACKAGE OUTLINE SOLDERING DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
1995 Jun 15
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Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
1 1.1 FEATURES PCF84CXXXA kernel
PCA84C646; PCA84C846
* Programmable active level polarities of VSYNC/HSYNC * Display RAM: 64 x 10-bit * Display character fonts: 64 (62 customized + 2 special reserved codes) * Display starting position: 64 different positions by software control, both vertical and horizontal * Character size: 4 different character sizes, line-by-line basis, 1 dot = 1H/1V, 2H/2V, 3H/3V, 4H/4V. (H: OSD clock period, V: number of horizontal scan line height) * Character matrix: 12 x 18 with no spacing between characters * Foreground colours: 8, character-by-character basis * Background colours: 8, word-by-word basis. Available when background is either in North-west shadowing, Box shadowing and Frame shadowing mode * Background/shadowing modes: 4, No background, North-west shadowing, Box shadowing, Frame shadowing (raster blanking), frame basis * On-chip oscillator for On Screen Display (OSD) function * Character blinking rate: 1 : 1, 1 : 3, 3 : 1 (frequency: 1 , 1 , 1 or 1 16 32 64 128 of fVSYNC, programmable), character basis * Display format: flexible display format by using Carriage Return (CR) code * Spacing between lines: 4 different choices, from 0, 4, 8 or 12 horizontal scan lines * Auto display character RAM address post increment when writing data * On-chip Power-on-reset * VSYNC leading edge can generate interrupt (programmable enable/disable by software) * 8-bit counter triggered by external pulse input.
* 8-bit CPU, ROM, RAM, I/O and derivative logic in one package * Over 80 instructions * All instructions of 1 or 2 cycles * Quasi-bidirectional standard I/O port lines (P0, P1) * Configuration of I/O lines individually selected by mask * External interrupt INT/T0 * 2 direct testable inputs T0, T1 * 8-bit timer/event counter * Single level vectored interrupt: external (INT), counter/timer, I2C-bus and VSYNC * Configuration of optimal on-chip oscillator transconductance by mask * On-chip oscillator clock frequency: 1 to 10 MHz * Power-on-reset and low-voltage detector * Low standby voltage and current in Idle and Stop modes * Single power supply: 4.5 to 5.5 V * Operating temperature: -20 to +70 C. 1.2 VST and OSD derivative
* 6 kbytes (PCA84C646) or 8 kbytes (PCA84C846) system ROM, 192 bytes system RAM * A multi-master I2C-bus interface * One 14-bit PWM output for VST * Three AFC inputs with 4-bit DAC and comparator * Four 6-bit PWM and four 7-bit PWM outputs (DACs for analog controls) * Eight port lines with 10 mA LED drive (at 1.2 V) capability
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Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
2 GENERAL DESCRIPTION
PCA84C646; PCA84C846
In addition to all these features a master-slave I2C-bus interface, 2 directly testable lines and an enhanced OSD facility for flexible screen format (maximum of 64 character types) are also provided. The on-chip Phase-Locked Loop (PLL) oscillator for OSD operation considerably reduces the radiation generated by the RC or LC oscillator. An 8-bit timer is integrated on-chip with a 5-bit prescaler. Another 8-bit counter with Schmitt-trigger input is used for clock/timer function application. Figure 1 shows the block diagram of the PCA84C646 and PCA84C846.
The PCA84C646 and PCA84C846 are 8-bit microcontrollers with enhanced OSD and VST functions. The PCA84C646 and PCA84C846 are members of the PCA84C640 CMOS microcontroller family. They include the PCF84CXXXA processor core, 6 or 8 kbytes of ROM and 192 bytes of RAM. I/O requirements are adequately catered for with 13 general purpose bidirectional I/O lines plus 16 function combined I/O lines. One 14-bit PWM analog control, 3 AFC inputs (4-bit DAC + comparator) for VST and four 6-bit and 7-bit PWM analog control outputs are provided. 3 ORDERING INFORMATION
PACKAGE TYPE NUMBER NAME PCA84C646P PCA84C846P SDIP42 DESCRIPTION plastic shrink dual in-line package; 42 leads (600 mil) VERSION SOT270-1
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4
1995 Jun 15
VOW0 INT / T0 VOB VOW1 C HSYNC T3 VOW2 VSYNC
handbook, full pagewidth
Philips Semiconductors
BLOCK DIAGRAM
T1
XTAL1 (IN)
CPU ON SCREEN DISPLAY
8-BIT COUNTER RAM 192 bytes
Microcontrollers for TV tuning control and OSD applications
XTAL2 (OUT)
8-BIT TIMER / EVENT COUNTER
ROM 6 kbytes (1) or 8 kbytes (2)
8-bit internal bus
5
4 x 6-BIT PWM 4 x 7-BIT PWM 8 PCF84CXXXA core excluding ROM / RAM 14-BIT DAC 8-BIT I/O PORTS
2
RESET
TEST / EMU
PARALLEL I/O PORTS
AFC 3 x 4-BIT DAC + COMPARATOR
I C-BUS INTERFACE
8 8 4 4
4
3
MED169
P00 P10 to P12 P14 to P07
DP00/PWM00 to DP07/PWM07
DP10 to DP13
DP20 to DP23
TDAC
AFC0 to AFC2
SDA
SCL
ROM size: (1) 6 kbytes for PCA84C646. (2) 8 kbytes for PCA84C846.
PCA84C646; PCA84C846
Preliminary specification
Fig.1 Block diagram
Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
5 5.1 PINNING INFORMATION Pinning
PCA84C646; PCA84C846
handbook, halfpage
VOB VOW2 DP22/VOW1 DP23/VOW0 VSYNC HSYNC P10/DXWR P11/DXRD DP13/TDAC P12/DXALE T3 P14/DXINT P00 P01 P02 P03 P04 P05 P06 P07 V SS
1 2 3 4 5 6 7 8 9 10
42 41 40 39 38 37 36 35 34 33
V DD C DP20/SDA DP21/SCL DP10/AFC0 DP11/AFC1 DP12/AFC2 INT/T0 T1 RESET
PCA84C646 32 11 XTAL2 PCA84C846
12 13 14 15 16 17 18 19 20 21
MED171
31 30 29 28 27 26 25 24 23 22
XTAL1 TEST/EMU DP00/PWM00 DP01/PWM01 DP02/PWM02 DP03/PWM03 DP04/PWM04 DP05/PWM05 DP06/PWM06 DP07/PWM07
Fig.2 Pin configuration PCA84C646P and PCA84C846P (SDIP42; SOT270-1).
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Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
5.2 Pin description
PCA84C646; PCA84C846
Table 1
Pin description for PCA84C646P and PCA84C846P; SDIP42 (see Fig.2) SYMBOL PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 to 20 21 29, 28, 27, 26, 25, 24, 23, 22 30 31 32 33 34 35 36 37 38 39 40 41 42 Derivative port line or I2C-bus clock line. Derivative port line or I2C-bus data line. External capacitor input for on chip PLL OSD oscillator. Power supply. Vertical synchronization signal input, active LOW. Horizontal synchronization signal input, active LOW. Port line 10 or emulation DXWR signal input. Port line 11 or emulation DXRD signal input. Derivative I/O port or 14-bit D/A PWM. Port line 12 or emulation DXALE signal input. Secondary 8-bit counter input pin (Schmitt-trigger). Port line 14 or emulation DXINT signal input. General I/O port lines (10 mA). Ground. Derivative I/O port; 6-bit PWM (PWM04 to 07) or 7-bit PWM (PWM00 to 03). Control input of testing and emulation mode, normally LOW. Oscillator input terminal for system clock. Oscillator output terminal for system clock. Initialize input, active LOW. Direct testable pin and event counter input. External interrupt/direct testable pin. Derivative I/O port or comparator input with 4-bit DAC. DESCRIPTION Video fast blanking output signal. Video character outputs or derivative port lines.
VOB VOW2 DP22/VOW1 DP23/VOW0 VSYNC HSYNC P10/DXWR P11/DXRD DP13/TDAC P12/DXALE T3 P14/DXINT P00 to P07 VSS DP00/PWM00 to DP07/PWM07 TEST/EMU XTAL1 XTAL2 RESET T1 INT/T0 DP12/AFC2 DP11/AFC1 DP10/AFC0 DP21/SCL DP20/SDA C VDD
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Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
6 RESET 7 7.1
PCA84C646; PCA84C846
ANALOG CONTROL 6 and 7-bit PWM outputs (PWM00 to PWM07)
The RESET pin is used as an active LOW input to initialize the microcontroller to a defined state. A Power-on-reset can be generated by using the RC-circuit as shown in Fig.3. An active reset can be generated by driving the RESET pin from an external logic device. Such an active reset pulse should not fall off before VDD has reached its fxtal-dependent minimum operating voltage. 6.1 Reset trip level
The PCA84C646/PCA84C846 has eight PWM outputs for analog controls of e.g. volume, balance, brightness and saturation. These PWM outputs generate pulse patterns with a repetition rate of 164 x fPWM or 1128 x fPWM. The analog value is determined by the ratio of the HIGH-time and the repetition time. A DC voltage proportional to the PWM control setting is obtained by means of an external integration network (low-pass filter). The eight PWM outputs are specified as follows: * PWM00 to PWM03 outputs with 7-bit resolution * PWM04 to PWM07 outputs with 6-bit resolution. Figure 4 shows the block diagram of the 6-bit or 7-bit PWM DAC. The polarity of the PWM0n output is selected as shown in Table 2 by the polarity control bit P6LVL/P7LVL (Derivative Register 23; see Table 25). The PWM0n output shares the pin with a DP0n I/O line under control of a PWMnE enable bit; for selection see Table 3. Figure 5 shows the 6 and 7-bit PWM0n output patterns (non-inverted; P6LVL/P7LVL = 0). The HIGH-time of a PWM0n output is tHIGH = [PWMnDL] x t0 where: [PWMnDL] = the contents of PWMn data latch (n = 0 to 7; Derivative Register 10 to 17; see Table 40) t0 = 1/fPWM; fPWM = 13 x fxtal. Table 2 Polarity selection for the PWM0n output POLARITY inverted not inverted Selection of pin function: DP0n/PWM0n (note 1) FUNCTION PWM0n output DP0n I/O
The RESET trip-voltage level is masked to 1.3 V in the PCA84C646 and PCA84C846. 6.2 Reset status
* Derivative Registers status; for details see Table 40 * Program Counter: 00H * Memory Bank: 00H * Register Bank: 00H * Stack Pointer: 00H * All interrupts disabled * Timer/event counter 1 stopped and cleared * Timer prescaler modulo-32 (PS = 0) * Timer flag cleared * Serial I/O interface disabled (ESO = 0) and in slave receiver mode * Idle and Stop mode cleared.
P6LVL/P7LVL
V DD R RESET ( 100 k) RESET C RESET V SS PCA84C646/846
MED172
1
(1)
internal reset
0 Table 3
PWMnE 1 0 Note
(1) To avoid overload of the internal diode, an external diode should be added in parallel if CRESET > 0.2 F.
1. n = 0 to 7.
Fig.3 External components for RESET pin.
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Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
PCA84C646; PCA84C846
handbook, full pagewidth
f PWM = f xtal 3
6 or 7-BIT PWM DATA LATCH
P6LVL/P7LVL (1-BIT)
DP0n data I/O
PWMnE
6 or 7-BIT DAC PWM CONTROLLER
Q Q DP0n/PWM0n
MED177
Fig.4 Block diagram of 6-bit or7-bit PWM DAC.
f xtal handbook, full pagewidth 3 64 or 128 00 1 2 3 m m+1 m+2 64 or 128 1
01
m
63 or 127
MLC261
decimal value PWM data latch
Fig.5 Example PWM0n output patterns (P6LVL/P7LVL = 0).
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Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
7.2 VST control 14-bit PWM DAC 7.2.1
PCA84C646; PCA84C846
COARSE ADJUSTMENT
The PCA84C646 and PCA84C846 have a PWM DAC output (TDAC) with a resolution of 16384 levels for Voltage Synthesized Tuning (VST). Figure 6 shows the block diagram of the 14-bit PWM DAC which consists of: * Two 7-bit DAC interface latches (see Table 40): - VSTH: Derivative Register 18; address 18H. - VSTL: Derivative Register 19; address 19H. * One 14-bit DAC data latch: VSTREG, which contents defines the HIGH-time. * 14-bit counter. * Pulse control. The contents of the interface latches VSTH and VSTL are latched into VSTREG. The upper seven bits of VSTREG are used for coarse adjustment, while the lower seven bits are used for fine adjustment. The contents of the interface latches VSTH and VSTL are latched into VSTREG at the beginning of the first tsub after VSTL is written (see Fig.7). After VSTH and VSTL are latched into VSTREG, it takes one tsub to generate the appropriate pulse pattern. Therefore, to ensure correct digital-to-analog conversion, two tsub periods should be allowed before beginning the next sequence (changing the contents of VSTH and VSTL). To ensure that the correct data is latched into VSTREG, VSTH must contain the correct value before VSTL is written; see the note in Fig.7. The repetition times of the pulse controllers are: * Coarse, upper seven bits (VSTH): t sub = 128 x 3 f xtal * Fine, lower seven bits (VSTL): t r = 128 x t sub = 49152 f xtal Output TDAC shares the same pin as DP13; bit TDACE (Derivative Register 22; see Table 22) selects the function of pin DP13/TDAC. Table 4 Selection of pin function DP13/TDAC FUNCTION TDAC; 14-bit PWM output DP13
An active HIGH pulse is generated in every subperiod; the pulse width being determined by the contents of VSTH. The coarse output (OUT1) is LOW at the start of each subperiod and will remain LOW during ( VSTH + 1 ) x 3 t s -----------------------------------------f xtal Where ts is the time within tsubn. The output will then go HIGH and remain HIGH until the start of the next subperiod. The coarse pulse width may be 3 calculated as: Pulse duration = ( 127 - VSTH ) x -------- . f xtal 7.2.2 FINE ADJUSTMENT
Fine adjustment is achieved by generating an additional pulse in specific subperiods. The pulse is added at the start of the selected subperiod and has a pulse width of 3/fxtal. The contents of VSTL determine in which subperiods a fine pulse will be added. It is the logic 0 state of the value held in VSTL that actually selects the subperiods. When more than one bit is a logic 0 then the subperiods selected will be a combination of those subperiods specified in Table 5. For example, if VSTL = 111 1010 then this is a combination of: * VSTL = 111 1110: subperiod 64 and * VSTL = 111 1011: subperiods 16, 48, 80 and 112. Pulses will be added in subperiods 16, 48, 64, 80 and 112. This example is illustrated in Fig.9. When VSTL holds 111 1111 fine adjustment is inhibited and the TDAC output is determined only by the contents of VSTH. Table 5 Additional pulse distribution ADDITIONAL PULSE IN SUBPERIOD 64 32 and 96 16, 48, 80 and 112 8, 24, 40, 56, 72, 88, 104 and 120 4, 12, 20, 28, 36, 44, 52...116 and 124 2, 6, 10, 14, 18, 22, 26, 30...122 and 126 1, 3, 5, 7, 9, 11, 13, 15, 17...125 and 127
VSTL 111 1110 111 1101 111 1011 111 0111 110 1111 101 1111 011 1111
TDACE 1 0
1995 Jun 15
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Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
PCA84C646; PCA84C846
Internal data bus `MOVE instruction' MSB DAC INTERFACE 7-BIT DATA LATCH (VSTH) LSB DAC INTERFACE 7-BIT DATA LATCH (VSTL) `MOV instruction'
7
7
DATA LOAD TIMING PULSE
LOAD
(1)
14-BIT DATA LATCH (VSTREG) 7 7 FINE ADDITIONAL PULSE GENERATOR OUT2
COARSE 7-BIT PWM OUT1
PWM output polarity control bit
ADD Q Q
TDAC output P14LVL Q14 to 8 14-BIT COUNTER
MED179
Q7 to 1 f TDAC = f xtal 3
(1) See Fig.7 for timing.
Fig.6 Block diagram of the 14-bit PWM DAC.
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Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
PCA84C646; PCA84C846
t sub CASE 1
t sub
t sub
VSTH
VSTL
VSTH,VSTL is loaded into VSTREG
CASE 2
t sub
t sub
t sub
VSTH
VSTL
VSTH,VSTL is loaded into VSTREG
t sub CASE 3
t sub
t sub
MED180
VSTL
VSTH,VSTL is loaded into VSTREG
VSTH
In CASE 1 and CASE 2, a new value for VSTH, VSTL is latched into VSTREG. In CASE 3, VSTL, together with an old value of VSTH are latched into VSTREG.
Fig.7 Latching VSTH, VSTL into VSTREG.
handbook, full pagewidth
tsubn 3/fxtal
f xtal 3 127 0 1 2 m m+1 m+2 127 0 1
00
(1)
01
(1)
m
(1)
127
MGC573
decimal value VSTH data latch ( VSTH + 1 ) x 3 (1) t s = -----------------------------------------f xtal
Fig.8 TDAC output (not inverted) with coarse adjustment only; VSTL = 1111111; P14LVL = 0.
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Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
PCA84C646; PCA84C846
tr
handbook, full pagewidth
t sub0
t sub16
t sub32
t sub48
t sub64
t sub80
t sub96
t sub112
t sub127
111 1110
111 1101
111 1011
111 1010
MCD314
VSTL
Fig.9 Fine adjustment output (OUT2).
handbook, full pagewidth
tsub16 3/fxtal
f xtal 3 127 0 1 2 m m+1 m+2 127 0 1
00
01
m
127
MGC572
decimal value VSTH data latch
VSTL = 111 1010; Additional pulses in subperiods 16, 48, 64, 80 and 112.
Fig.10 Example of TDAC (not inverted) output pulses for several values of VSTH (tsub16). 1995 Jun 15 13
Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
8 AFC INPUT
PCA84C646; PCA84C846
If the compare bit: * AFCC = 0, then the AFC voltage < Vref. * AFCC = 1, then the AFC voltage > Vref. Table 6 BIT AFCE2 AFCE1 AFCE0 Selection of pin function DP1i/AFCi (i = 0, 1, 2) VALUE 1 0 1 0 1 0 Table 7 PIN FUNCTION DP12 AFC2 DP11 AFC1 DP10 AFC0 COMPARATOR disabled enabled disabled enabled disabled enabled
The AFC input is intended to measure the level of the Automatic Frequency Control (AFC) signal. This is done by comparing the AFC signal with the output of a 4-bit digital-to-analog converter as shown in Fig.11. The DAC analog switches select one of the 16 resistor taps that are connected between VDD and VSS (controlled by bits AFCV3, AFCV2, AFCV1, AFCV0; Derivative Register 20). The AFCC signal (bit 0 in Derivative Register 20) then can be tested to check whether the AFC input is higher or lower than the DAC level. The AFC inputs AFC0, AFC1 and AFC2 share the same pins as Derivative Port lines DP10, DP11 and DP12. The pin functions are selected by bits AFCE0, AFCE1, AFCE2 (AFC enable/disable bits; Derivative Register 22); for selection see Table 6. AFCH1 and AFCH0 (Derivative Register 20) select one out of three AFC inputs to the comparator; for a correct comparison, enable the corresponding AFC input (AFCi) as shown in Table 7. The conversion time of the AFC is greater than 6 s but less than 9 s. It is recommended to add a NOP instruction between the instruction which changes Vref or channel selection and the instruction which reads the AFCC bit (compare bit).
AFC input selection SELECT AFC Channel 0; AFC0 AFC Channel 1; AFC1 AFC Channel 2; AFC2 reserved
AFCH1 AFCH0 0 0 1 1 0 1 0 1
handbook, full pagewidth
(DP10 to DP12) EN0 DP10/AFC0 DP11/AFC1 DP12/AFC2 AFC ANALOG SELECTOR EN1 EN2
Internal bus
COMPARATOR EN
`MOV A, D20' instruction to read AFCCx bit
Channel selection
AFCH1
AFCH0
ENABLE SELECTOR 4-BIT D/A
AFCE0
AFCE1
AFCE2 AFCV3 AFCV2 AFCV1 AFCV0
MED185
AFC function enable selection
AFC value selection
Fig.11 AFC circuit.
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Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
Table 8 AFCV3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Vref as a function of AFCV3 to AFCV0 AFCV2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 AFCV1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 AFCV0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Vref VDD x 116 VDD x 216 VDD x 316 VDD x 416 VDD x 516 VDD x 616 VDD x 716 VDD x 816 VDD x 916 VDD x 1016 VDD x 1116 VDD x 1216 VDD x 1316 VDD x 1416 VDD x 1516 VDD
PCA84C646; PCA84C846
Vref (VDD = 5.0 V) 0.31 V 0.62 V 0.93 V 1.25 V 1.56 V 1.87 V 2.18 V 2.50 V 2.81 V 3.12 V 3.43 V 3.75 V 4.06 V 4.37 V 4.68 V 5.00 V
1995 Jun 15
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Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
9 9.1 OSD (ON SCREEN DISPLAY) FUNCTION Features 9.3
PCA84C646; PCA84C846
Vertical display position control
* Display RAM: 64 x 10 bit. * Display character fonts: 64 (in which 62 customized + 2 special reserved codes). * Display starting position (of the first character): 64 different positions by software control, both vertical and horizontal. * Character size: 4 different character sizes, line-by-line basis, 1 dot = 1H/1V, 2H/2V, 3H/3V, 4H/4V. * Character matrix: 12 x 18 with no spacing between characters. * Foreground colours: 8, combination of Red, Green, Blue; character-by-character basis. * Background/shadowing modes: 4, No background, Box shadowing, North-west shadowing, Frame shadowing (raster blanking), frame basis. * Background colours: 8, combination of Red, Green, Blue; word-by-word basis. Available when background mode is either in Box shadowing or North-west shadowing and Frame shadowing mode. * On-chip OSD oscillator. * Character blinking rate: 1 : 1, 1 : 3, 3 : 1 (frequency: 1 , 1 , 1 or 1 16 32 64 128 of fVSYNC, programmable, e.g. NTSC: 6016 Hz, PAL: 5064 Hz etc.); character basis. * Display format: flexible display format by using Carriage Return (CR) code, maximum number of characters per line is flexible and depending on the OSD clock. * Spacing between lines: 4 different choices from 0, 4, 8 or 12 horizontal scan lines. * Display character RAM auto-address-post-increment when writing data. * Programmable HSYNC and VSYNC active input polarity. * Programmable G (VOW1), B (VOW2), R (VOW0) and FB (VOB) output polarity. 9.2 Horizontal display position control
The vertical position counter is increased every HSYNC cycle and is reset by the VSYNC signal. Vertical start position is controlled by Derivative Register 35 (VPOS; see Table 34). The vertical starting position is calculated as: VP = [4 x (V5 to V0)] x (horizontal scan lines) where (V5 to V0) = decimal value of register VPOS; (V5 to V0) 0. 9.4 Clock generator
Figure 12 illustrates the block diagram of the on-chip OSD clock generator which consists of a Phased-Lock Loop (PLL) circuit. The Voltage Controlled Oscillator (VCO) outputs a clock (fVCO) with a frequency range of 8 to 20 MHz (see Fig.12). The input signal f1 = HSYNC. The programmable active level detector: * Passes signal f1, when HSYNC is active HIGH, or * Inverts signal f1, when HSYNC is active LOW. The output signal f2 is always active HIGH. The VCO is synchronized with the HIGH-to-LOW edge of the f2 signal. The value programmed in the 7-bit PLL Programmable Counter control register (PLLCN; Derivative Register 25; see Table 40) determines: fVCO = f1 x 16 x (decimal value of 7-bit counter); where 16 < (decimal value of 7-bit counter) < 48. The value 16 is the 4-bit prescaler which increases or decreases the output of the VCO in steps of (16 x f1). Given an example of f1 = 15.750 kHz, the fVCO is then increased or decreased in steps of 16 x 15.750 kHz = 252 kHz = 0.25 MHz. The fVCO is fed into a buffer to generate the OSD dot clock frequency signal (fOSD); 4 MHz fOSD 12 MHz. Decreasing fOSD gives broader characters. Recommended: 4 MHz fOSD typical 12 MHz. The OSD clock is enabled/disabled by the state of the EN bit (Derivative Register 34; see also Section 12.4). When the OSD clock is disabled (fOSD = LOW) the oscillator remains active, therefore the transient time from the OSD clock start-up to locking into the external HSYNC signal is reduced. As the on-chip oscillator is always active after Power-on, when the OSD clock is enabled no large currents flow (as for RC or LC oscillators) and therefore radiated noise is dramatically reduced.
The horizontal position counter is increased every OSD clock (fOSD) cycle after the programmed level of HSYNC occurs at the HSYNC pin and is reset when the opposite polarity of the HSYNC is reached. Horizontal start position is controlled by Derivative Register 36 (HPOS; see Table 36). The starting position is calculated as: HP = [4 x (H5 to H0) + 5] x (OSD clock cycle) where (H5 to H0) = decimal value of register HPOS; (H5 to H0) 10. 1995 Jun 15 16
Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
9.4.1 MOUNTING PRECAUTIONS
PCA84C646; PCA84C846
* Position microcontroller optimal and away from components bearing high voltage and/or strong current. * PLL loop filter ground of capacitors Cs and Cp must be directly connected to the VSS pin (21). Avoid a ground loop and separate the ground from other digital signals ground. * The connection between VSS pin (21) and +5 V regulator ground/switching power supply secondary ground must be as short as possible.
To achieve good OSD performance, take the following precautions for the microcontroller mounting: * Apply the recommended R, Cs and Cp (PLL loop filter) values as shown in Fig.12 and place them as close as possible to pin C (41). * To guarantee stable PLL operation, apply a noise-free HSYNC signal (pin 6). * Avoid heavy loading of the output pins. * The supply voltage (VDD) must be correctly decoupled. Connect decoupling capacitors as close as possible to the VDD and VSS pins.
handbook, full pagewidth
f1
f2
STANDBY
HSYNC
ACTIVE LEVEL DETECTOR
PHASE/ FREQUENCY DETECTOR divided by N
CHARGE PUMP AND LOOP FILTER
C R Cs
(1)
Cp
(2)
PROGRAMMABLE 7-BIT COUNTER
16
f VCO
VOLTAGE CONTROLLED OSCILLATOR fOSD (OSD clock)
OSD disable (1) R = 10 to 47 k; typ. 15 k. Cs = 100 to 470 nF; typ. 220 nF. Cp = 110 Cs. For mounting see Section 9.4.1 "Mounting precautions". (2) Example: If f1 = 15.750 kHz and (decimal value of 7-bit counter) = 32 then fVCO = 8.064 MHz and the output of the Programmable 7-bit counter is 15.750 kHz.
MED196
Fig.12 On-chip OSD oscillator.
1995 Jun 15
17
PCA84C646; PCA84C846
Preliminary specification
Fig.13 OSD block diagram.
handbook, full pagewidth
1995 Jun 15
Philips Semiconductors
CPU bus
Microcontrollers for TV tuning control and OSD applications
CHARACTER SIZE CONTROL
COUNTER WRITE ADDRESS
ADDRESS BUFFER SELECTOR CONTROL REGISTER
DISPLAY CHARACTER RAM
HORIZONTAL POSITION REGISTER/ COUNTER VERTICAL POSITION REGISTER/ COUNTER control signals DISPLAY BIT PATTERN ROM(64)
C
ON-CHIP OSCILLATOR
18
INTERNAL SYNCHRONOUS CIRCUIT
INSTRUCTION DECODER CONTROL REGISTER
DISPLAY CONTROL AND OUTPUT STAGE R G B FB
MED189
HSYNC
VSYNC
VOW1 VOW0 VOW2 VOB
Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
10 DISPLAY RAM ORGANIZATION The display RAM is organized as 64 x 10 bits. The general format of each RAM location is as follows: * Bits <9-4> hold data, comprising: - Customer designed Character Font Codes (62) - Carriage Return Code (1) - Space Code (1). * Bits <3-0> contain the attributes of the Character Font: - Foreground colour and Blinking - Character size and Line space - Background colour and End-of-Display . Table 9 9 C5 Format of Character Font Code 8 C4 7 C3 6 C2 5 C1 4 C0 10.1
PCA84C646; PCA84C846
Description of display RAM codes
There are three data formats for the display RAM code 1. Character Font Code 2. Carriage Return Code 3. Space Code. The three data formats and their descriptions are shown in Tables 9 to 17. Figure 14 illustrates an example of the timing of FB, R, G, and B pulses when displaying a line of dots stream in a character. FB = VOB; R = VOW0, G = VOW1; B = VOW2. Figure 15 shows an example of the screen which includes some Cariage Return and Space codes.
3 T3
2 T2 Foreground colour
1 T1
0 T0 Blink
Character Font Code (00H - 3DH) Table 10 Description of Character Font Code bits SYMBOL C5 to C0 T3 to T1 T0 DESCRIPTION
If bits <9-4> are in the range (00H to 3DH), then this is a Character Font Code and 1 from 62 customer designed character fonts can be selected. Bits <3-1> determine the (Foreground) colour (1 out of 8) of this character; see Table 11. Blinking of this character is controlled by bit <0>. See Section 12.3 for duty cycle and frequency control. When T0 = 0; blinking is OFF. When T0 = 1; blinking is ON. Blinking rate: 116, 132, 164 or 1128 x fVSYNC.
Table 11 Selection of Background and Foreground colour T3 (RED) 0 0 0 0 1 1 1 1 T2 (GREEN) 0 0 1 1 0 0 1 1 T1 (BLUE) 0 1 0 1 0 1 0 1 black blue green cyan red magenta yellow white COLOUR
1995 Jun 15
19
Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
Table 12 Format of Carriage Return Code 9 C5 8 C4 7 C3 6 C2 5 C1 4 C0
PCA84C646; PCA84C846
3 T3
2 T2
1 T1
0 T0
Carriage Return Code (3EH)
Character size
Line Spacing
Table 13 Description of Carriage Return Code bits; format is shown in Table 12 SYMBOL C5 to C0 DESCRIPTION If bits <9-4> hold 3EH, then this is the Carriage Return Code. The current display line is terminated (a transparent pattern appears on the screen) and the next character will be displayed at the beginning of the next line. Bits <3-2> select the size of the of the character to be displayed on the next line; see Table 14. Bits <1-0> determine the spacing between lines of displayed characters. Spacing is a multiple of the number of horizontal scan lines. In order to prevent vertical jumping of the display, the first line should be a non-displayed line i.e. the Carriage Return Code. The line spacing for this code must not be zero; see Table 15. Table 15 Selection of line spacing T1 0 0 1 1 T0 0 1 0 1 LINE SPACING 0H line 4H line 8H line 12H line
T3 to T2 T1 to T0
Table 14 Selection of character size T3 0 0 1 1 Note 1. H is the OSD clock period; V is the number of horizontal scan lines per dot. Table 16 Format of Space Code 9 C5 8 C4 7 C3 6 C2 5 C1 T2 0 1 0 1 CHARACTER DOT SIZE(1) 1H/1V 2H/2V 3H/3V 4H/4V
4 C0
3 T3
2 T2 Background colour
1 T1
0 T0 End
Space Code (3FH) Table 17 Description of Space Code bits; format is shown in Table 16 SYMBOL C5 to C0 T3 to T1 DESCRIPTION
If bits <9-4> hold 3FH, then this is the Space Code. A transparent pattern, equal to one character width, will be displayed on the screen. Bits <3-1> determine the background colour of the characters including the Space Code in Box shadowing mode but following the Space Code in North-west shadowing mode. See Section 12.4 for more details. Background colour selection is the same as Foreground colour selection; see Table 11. Bit <0> is the End-of-Display bit and indicates the end of display of the current screen before exhaustion of display RAM. The last character displayed on the TV screen is either the 64th RAM location or a Space Code with the End-of-display attribute set to logic 1. When T0 = 0; continue display of next character. When T0 = 1; end of display.
T0
1995 Jun 15
20
Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
PCA84C646; PCA84C846
handbook, full pagewidth
SP code R G B I FB ACM
SP code
MED204
"S" : red colour "I" : green colour "Z" : G+B+I colour
"E" : B+I colour 1st SP code : ACM = on 2nd SP code : ACM = off
Fig.14 R, G, B and FB timing.
handbook, full pagewidth
Vstart
H I ! SP T H I S SP I S CR
line spacing 1 = 4H
CR
line spacing 2 = 8H
T H E SP N E W CR F U N C T I O N CR I N SP P C F 8 5 C X X X
Hstart
line spacing 3 = 0H line spacing 4 = 0H
CR
line spacing 4 = 4H
St
SP
a
n
CR
d
a
l
CR
line spacing 6 = 0H
WEL
COME
Volume
Channel
MED205
Four different background colours (in box shadowing mode): Black Red Green Blue
Fig.15 On-screen-display (an example).
1995 Jun 15
21
Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
10.2 Loading character data into display RAM
PCA84C646; PCA84C846
2. Load the character attributes into DCRTR. If the attributes of a series of displayed characters are the same, only DCRCR needs to be updated. The meaning of the attributes (4 bits) is dependent on the contents of the next command (the data in the DCRCR bits <5-0>; i.e. Carriage Return Code, Space Code or Character Font Code). 3. Load the character data into DCRCR. This operation loads the selected RAM location with the data held in registers DCRTR and DCRCR. The address held in DCRAR is then incremented by `1' pointing to the next RAM location in anticipation of the next operation. Overflow of the DCRAR, i.e. overflow from 63 to 64, makes it reset to zero. After the instruction `MOV D32H, A' is finished, the post-increment operation is performed automatically. Auto-post-increment operation: Begin (DCRAR) (DCRAR) + 1 If (DCRAR) > 63 then (DCRAR) 0 End
Three Derivative Registers are used to address and load data into the display RAM. These registers (configurations are shown in Tables 18, 19 and 20) are described in the following Sections. 10.2.1 DCR ADDRESS REGISTER (DCRAR)
Table 18 DCRAR (address 30H) 7 - 6 - 5 A5 4 A4 3 A3 2 A2 1 A1 0 A0
This is Derivative Register 30 and bits <5-0> holds the address of the location in display RAM to which the data held in registers DCRTR and DCRCR will be written to. Bits <7-6> are reserved. 10.2.2 DCR ATTRIBUTE REGISTER (DCRTR)
Table 19 DCRTR (address 31H) 7 - 6 - 5 - 4 - 3 T3 2 T2 1 T1 0 T0
After master RESET the initial values of DCRAR, DCRTR and DCRCR are all zero. Figure 16 shows how DCRAR is incremented and advanced.
This is Derivative Register 31 and holds the character font attribute data. The data will be loaded into bits <3-0> of the location in RAM pointed to by the contents of DCRAR. Bits <7-4> are reserved. 10.2.3 DCR CHARACTER REGISTER (DCRCR)
handbook, halfpage DCRAR 00
01 62
02 61
03
04 19
17 18
MED208
63
Table 20 DCRCR (address 32H) 7 - 6 - 5 C5 4 C4 3 C3 2 C2 1 C1 0 C0 10.4 This is Derivative Register 32 and holds the character data that will be loaded into bits <9-4> of the location in RAM addressed by the contents of DCRAR. Bits <7-6> are reserved. 10.3 Writing character data to display RAM Default value of the display character Fig.16 DCRAR increment cycle.
The default values of the display characters, after master RESET, are as follows: * Background colour = Blue (R = 0, G = 0, B = 1) * Character size = 1V/1H * End-of-Display control bit = 0. If another set-up is needed, the first character should be SP code and second character is CR code to define the character size and background colour.
1. Select the start address in display RAM. The start address is stored in DCRAR and can take any value between 0 and 63.
1995 Jun 15
22
Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
11 CHARACTER ROM Each character font is stored in the on-chip character ROM in a 12 x 19 dot matrix. However, only elements in Rows 1 to 18 (12 x 18 dot matrix) can be selected as visible dots on the screen. Row 0 is only used for the combination of two characters in a vertical direction when North-west shadowing mode is selected (for details see Section 12.4). Row 0 contains the same bit pattern of Row 18 of the character above it. If no combined character in vertical direction is intended for this character, Row 0 should be filled with all zeros. 11.1 Character ROM organization
PCA84C646; PCA84C846
generates the bit pattern HEX files is available on request. The package is run under the MS-DOS environment for IBM compatible PCs. Regarding Fig.17 the following points should be noted. 1. Row 0 of each font is reserved for vertical combination of two fonts. 2. Binary 1 denotes visual dots. 3. ROM1 and ROM2 data files are in INTEL hex format on a byte basis. Each byte is structured High nibble followed by Low nibble. 4. The unused last byte of each font in ROM1 must be filled with FFH. 5. The unused last 212 bytes in ROM2 must be filled with the same data as held in the corresponding address in ROM1. 6. The data bytes of the last 2 reserved fonts (Carriage Return and Space Codes) should be filled with 00H. 7. CS denotes Checksum.
ROM is divided into two parts: ROM1 and ROM2. The organization of the bit patterns stored in ROM1 and ROM2 and the file format to submit to Philips for customized character sets is shown in Fig.17. A software package (OSDGEM) that assists in the design of character fonts on-screen and that also automatically
Column
MLB760
MSB
LSB
handbook, full pagewidth
0 1 2 3 4 5 6
11 10 9 8 7 6 5 4 3 2 1 0 000 ROM1 3 F C ROM2 2 2 0 ROM1 2 2 0 ROM2 3 F C ROM1 220 220 ROM2 ROM1
ROM1
000
ROM2
3FC
220 220 3FC 220 220 3FC 220 220 3FF 001 001 553 552 006 00C 058 030
ROW
7 8 9 10 11 12 13 14 15 16 17 18
3 F C ROM2 2 2 0 ROM1 2 2 0 ROM2 3FF 001 001 553 552 006 00C 058 030 ROM1 ROM2 ROM1 ROM2 ROM1 ROM2 ROM1 ROM2 ROM1
ROM1
byte # 0 1 __ __ __ __ 89ABCD __ __ 2 3 4 5 6 __7 __ __ __ __ __ __ : 1 0 0 0 0 0 0 0 00 00 22 FC 03 22 20 F2 3F 01 20 55 0C 00 :10001000 <--:10002000 <--DATA FOR FONT 2 DATA FOR FONT 3 - - - 12 - - - 56
E __ 03
F __ FF CS CS CS
34> F F 78> F F
ROM2
: 1 0 0 0 0 0 0 0 FC 03 22 20 C2 3F 20 12 00 53 65 00 58 :10001000 <--:10002000 <--DATA FOR FONT 2 DATA FOR FONT 3 ---> --->
Fig.17 Font pattern stored in character ROM1 and ROM2.
> > >
0 0 03 1 X 34 5 X 78 FF FF FF CS CS CS
1995 Jun 15
23
Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
12 OSD CONTROL REGISTERS
PCA84C646; PCA84C846
The functions of the OSD circuitry are controlled by the Derivative Registers as shown in Table 21. Table 21 OSD Control Registers overview DERIVATIVE REGISTER NAME NUMBER CON1 CON2 CON3 CON4 22 23 33 34 ADDR 22H 23H 33H 34H Enable TDAC; the I2C-bus lines; the AFC functions and the VOW0 and VOW1 lines. Selects the output polarity of the PWM outputs and also enables and selects the VSYNC interrupt. Selects the blinking frequency and the active ratio of the blinking frequency for the OSD. Selects the 4 display modes; the active state of HSYNC and VSYNC and the output polarity of the FB and VOW0 to VOW2 outputs. It also enables/disables the OSD clock. Selects the vertical starting position of the display row. Selects the horizontal starting position of the display row. Selects the background colour. FUNCTION
VPOS HPOS BCC
35 36 37
35H 36H 37H
1995 Jun 15
24
Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
12.1 Derivative Register 22 (CON1)
PCA84C646; PCA84C846
Table 22 Derivative Register 22 (address 22H) 7 TDACE 6 SCLE 5 SDAE 4 ADC2E 3 ADC1E 2 ADC0E 1 VOW1E 0 VOW0E
Table 23 Description of Derivative Register 22 bits BIT 7 SYMBOL TDACE DESCRIPTION Pulse Width Modulated output TDAC enable bit. When: TDACE = 1; pin DP13/TDAC is selected as output TDAC. TDACE = 0; pin DP13/TDAC is selected as Derivative Port line DP1. 6 SCLE I2C-bus clock enable bit. When: SCLE = 1; pin DP21/SCL is selected as SCL (I2C-bus clock line). SCLE = 0; pin DP21/SCL is selected as Derivative Port line DP21. 5 SDAE I2C-bus data enable bit. When: SDAE = 1; pin DP20/SDA is selected as SDA (I2C-bus data line). SDAE = 0; pin DP20/SDA is selected as Derivative Port line DP20. 4 3 2 1 AFCE2 AFCE1 AFCE0 VOW1E Pin function selection bit. When: VOW1E = 1; pin DP22/VOW1 is selected as VOW1. VOW1E = 0; pin DP22/VOW1 is selected as Derivative Port line DP22. 0 VOW0E Pin function selection bit. When: VOW0E = 1; pin DP23/VOW1 is selected as VOW1. VOW0E = 0; pin DP23/VOW1 is selected as Derivative Port line DP23. These 3 bits select the pin function of DP1i/AFC and enable/disable the comparator in the AFC circuit; for the selection and enable/disable function see Table 7.
1995 Jun 15
25
Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
12.2 Derivative Register 23 (CON2)
PCA84C646; PCA84C846
Table 24 Derivative Register 23 7 VINT 6 VIEN 5 - 4 - 3 - 2 P14LVL 1 P7LVL 0 P6LVL
Table 25 Description of Derivative Register 23 bits BIT 7 6 SYMBOL VINT VIEN DESCRIPTION Bit VINT indicates if the interrupt comes from VSYNC (if VINT = 1 and VIEN = 1) or I2C-bus when the CPU gets interrupted by interrupt vector address 7. The VSYNC leading edge (active level detection automatically done by the PCA84C646/PCA84C846) generates an interrupt if bit VIEN = 1 and the SIO interrupt is enabled (i.e. the I2C-bus and the VSYNC interrupt shares the same interrupt vector). These three bits are reserved. Polarity select bit for output TDA. When: P14LVL = 1; the TDAC output is inverted. P14LVL = 0; the TDAC output is not inverted. 1 P7LVL Polarity select bit for outputs PWM00 to PWM03. When: P7LVL = 1; the outputs PWM00 to PWM03 are inverted. P7LVL = 0; the outputs PWM00 to PWM03 are not inverted. 0 P6LVL Polarity select bit for outputs PWM04 to PWM07. When: P6LVL = 1; the outputs PWM04 to PWM07 are inverted. P6LVL = 0; the outputs PWM04 to PWM07 are not inverted.
5 to 4 2
- P14LVL
1995 Jun 15
26
Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
12.3 Derivative Register 33 (CON3)
PCA84C646; PCA84C846
Derivative Register 33 is to control the character blinking related operation. Figure 18 shows the timing diagram of character blinking frequency and blinking ratio. Table 26 Derivative Register 33 7 - 6 - 5 - 4 - 3 BR1 2 BR0 1 BF1 0 BF0
Table 27 Description of Derivative Register 33 bits BIT 7 to 4 3 2 1 0 SYMBOL - BR1 BR0 BF1 BF0 These 4 bits are reserved. Blinking active ratio select bits. These two bits allow one from a choice of three active blinking ratios to be selected; see Table 28. Blinking frequency select bits. These two bits allow one from a choice of four blinking frequencies to be selected. f VSYNC Blinking frequency = --------------------------------------- Hz , ( BF1, BF0 ) 16 x 2 where `2(BF1, BF0)' is a decimal value determined by bits BF1 and BF0; see Table 29. Table 28 Active ratio determined by bits BR1 and BR0 BR1 0 0 1 1 BR0 0 1 0 1 ACTIVE RATIO 3 : 1 (default) 1:1 1:3 reserved Table 29 Blinking frequency determined by (BF1,BF0) BF1 BF0 2(BF1, BF0) 0 0 1 1 0 1 0 1 1 2 4 8
1
DESCRIPTION
BLINKING FREQUENCY (Hz)
1 16 1 32 1 64
x fVSYNC x fVSYNC x fVSYNC
128 x fVSYNC (default)
handbook, full pagewidth
60 Hz VSYNC 0 1 23 7 8 10 11
60 Hz
14 15 0
1
2
3
7
8
10 11
14 15
Blinking frequency: Blinking ratio: 1 : 3 Blinking frequency: Blinking ratio: 1 : 1
f VSYNC 16 f VSYNC
16 f Blinking frequency: VSYNC 16 Blinking ratio: 3 : 1 f Blinking frequency: VSYNC 32 Blinking ratio: 1 : 3 f Blinking frequency: VSYNC 32 Blinking ratio: 1 : 1 f Blinking frequency: VSYNC 32 Blinking ratio: 3 : 1
MRA848
Fig.18 Example of character blinking (NTSC 525LPF/60Hz).
1995 Jun 15
27
Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
12.4 Derivative Register 34 (CON4)
PCA84C646; PCA84C846
This register selects the 4 display modes(Mode 0 to Mode 3); the active state of HSYNC and VSYNC and the output polarity of the FB and VOW0 to VOW2 outputs. It also enables/disables the OSD clock (fOSD). Table 30 Derivative Register 34 7 - 6 - 5 S1 4 S0 3 Hp 2 Vp 1 Bp 0 EN
Table 31 Description of Derivative Register 34 bits BIT 7 6 5 4 3 SYMBOL - - S1 S0 Hp HSYNC signal polarity control bit (see Fig.19). When Hp = 1; the active level of HSYNC is HIGH. When Hp = 0; the active level of HSYNC is LOW (default state). 2 Vp VSYNC signal polarity control bit (see Fig.19). When Vp = 1; the active level of VSYNC is HIGH. When Vp = 0; the active level of VSYNC is LOW (default state). 1 Bp Output polarity control bit for FB, VOW0, VOW1 and VOW2 (see Fig.20). When Bp = 1; the polarity of FB, VOW0, VOW1 and VOW2 is HIGH (default state). When Bp = 0; the polarity of FB, VOW0, VOW1 and VOW2 is LOW. 0 EN OSD clock enable/disable bit. When EN = 1; the OSD clock is enabled. When EN = 0; the OSD clock is disabled. Table 32 Selection of Display Modes S1 0 0 S0 0 1 DISPLAY MODE Mode 0 No background mode (see Fig.21). The OSD fonts/characters are directly superimposed on the TV video signals. Mode 1 North-west shadowing mode (see Fig.22). Available only in the character size 2V/2H or 4V/4H (V: horizontal line; H: OSD clock).The shadows of the characters are generated by placing a light source on the North-west 45 degree direction (see also Figs 25 and 26). When designing the character bit pattern, care must be taken that the shadows generated by this mode is only within the cell boundary in vertical direction (see Figs 28 and 29 for details). But shadows generated by this mode in horizontal direction has no boundary limitation (Fig.30). Mode 2 Box shadowing mode (see Fig.23). Box shadowing is to surround the character font by a 12 x 18 dots box in background, i.e. within the character font cell; locations with no foreground dots are filled with background dots (see Fig.27). Mode 3 Frame shadowing mode (raster blanking; see Fig.24); background colour displayed on full screen where no bit patterns are on.The background colour is controlled by Derivative Register 37 and has 8 different colours; see Table 39. Display mode select bits; see Table 32. These two bits are reserved. DESCRIPTION
1
0
1
1
1995 Jun 15
28
Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
PCA84C646; PCA84C846
handbook, full pagewidth
HSYNC/VSYNC pin Hp/Vp = 0 (active LOW)
character display interval
Hp/Vp = 1 (active HIGH) HSYNC/VSYNC pin
character display interval
MED195
Fig.19 Bits Hp/Vp determine the active level of the HSYNC/VSYNC signal.
handbook, full pagewidth
FB (R, G, B ) Bp = 0 (active LOW) character display interval character display interval
Bp = 1 (active HIGH) FB ( R, G, B )
MED194
Fig.20 Bit Bp determines the active level of FB, R, G and B.
1995 Jun 15
29
Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
PCA84C646; PCA84C846
MOS
SP code
SP code
FB R G B I
Suppose the colour of each character is as follows: "M" -- (R+B) "O" -- (B) "S" -- (R+G)
MED211
Fig.21 Mode 0: No Background (superimpose) mode.
1995 Jun 15
30
Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
PCA84C646; PCA84C846
handbook, full pagewidth
: background colour FB R G B
MED212
Assume : 1. 1st char in (G+B) colour 2. 2nd char in (G+B) 3. background colour : R+B
1DOSC
Available only in character size 2V/2H or 4V/4H.
Fig.22 Mode 1: North-west shadowing mode.
1995 Jun 15
31
Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
PCA84C646; PCA84C846
handbook, full pagewidth
Column 0
Column 11
Row 0
Row 17
MED213
background colour
Fig.23 Mode 2: Box shadowing mode.
1995 Jun 15
32
Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
PCA84C646; PCA84C846
handbook, full pagewidth
Background colour = BLUE
MED214
Fig.24 Mode 3: Frame shadowing mode.
1995 Jun 15
33
Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
PCA84C646; PCA84C846
handbook, full pagewidth
0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
1
2
3
4
5
6
7
8
9
10
11
1V
MED215
1H
Fig.25 Example of North-west shadowing mode; size = 2V/2H.
1995 Jun 15
34
Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
PCA84C646; PCA84C846
handbook, full pagewidth
0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
1
2
3
4
5
6
7
8
9
10
11
2V
MED216
2H
Fig.26 Example of North-west shadowing mode; size = 4V/4H.
1995 Jun 15
35
Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
PCA84C646; PCA84C846
size = 1
size = 2
size = 4 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
MED217
1
2
3
4
5
6
7
8
9
10
11
size = 3
Fig.27 Example of Box shadowing mode.
1995 Jun 15
36
PCA84C646; PCA84C846
Preliminary specification
Fig.28 Example 1: North-west shadowing mode; shadow within cell boundary.
handbook, full pagewidth
1995 Jun 15
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
MED218
Philips Semiconductors
0
1
2
3
4
5
Microcontrollers for TV tuning control and OSD applications
6
7
8
9
37
10
11
12
13
14
15
16
17
18
Character designed in character ROM
Character displayed on TV screen
PCA84C646; PCA84C846
Preliminary specification
Fig.29 Example 2: North-west shadowing mode; shadow out of cell boundary.
handbook, full pagewidth
1995 Jun 15
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
MED219
0
Philips Semiconductors
1
2
3
4
5
Microcontrollers for TV tuning control and OSD applications
6
7
8
9
10
38
11
12
13
14
15
16
17
18
Character designed in character ROM
Character displayed on TV screen
Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3
PCA84C646; PCA84C846
4
5
6
7
8
9
10
11
Two characters designed in character ROM separately
(1)
0 0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9 10 11
(2)
(2)
10 11 12 13 14 15 16 17
MED220
Two characters displayed on TV screen
(1) Horizontal shadowing overflow into the next character cell.
Cell boundary
(2) Vertical shadowing overflow does not show beyond the bottom of a cell.
Fig.30 North-west shadowing.
1995 Jun 15
39
Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
12.4.1 SPACE CODE AND CARRIAGE RETURN CODE IN
DIFFERENT BACKGROUND/SHADOWING MODES
PCA84C646; PCA84C846
Mode 3 Frame shadowing mode. The Space Code and Carriage Return code is displayed as a transparent pattern with background colour; see Table 39. Space Code and Carriage Return Code in the 4 different background/shadowing modes (0 to 3), with: * Blinking OFF are shown in Figs 31, 32, 33 and 34. * Blinking ON are shown in Figs 36, 37, 38 and 39. Figure 39 shows blinking of a character only within the 12 x 18 cell boundary. If the shadow of the blinking character crosses over the boundary of the cell of the character next to the one that is not blinking, the shadow dot will still appear on the screen regardless whether the blinking character is ON or OFF.
Mode 0 No background mode. Both the Space Code and the Carriage Return Code are displayed as transparent (no bit) patterns, with the video signal as the background. Mode 1 North-west shadowing mode. Similar to Mode 0. Mode 2 Box shadowing mode. The Space Code is displayed as a transparent pattern with selected background colour. This will also be the background colour of the character following the Space Code. However, when the Space Code is used as an end bit, it will be displayed as a transparent pattern superimposed on the video. The Carriage Return Code in Mode 2 is also displayed as a transparent pattern superimposed on the video signal.
handbook, full pagewidth
0 1 2 3 4 5 6 7 8 910 11 0 1 2 3 4 5 6 7 8 910 11 0 1 2 3 4 5 6 7 8 910 11 0 1 2 3 4 5 6 7 8 910 11 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
SP code
CR code
Red colour Blue colour
MED227
Fig.31 SP and CR codes in Mode 0: No background mode (superimpose; transparent pattern).
1995 Jun 15
40
Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
PCA84C646; PCA84C846
handbook, full pagewidth
0 1 2 3 4 5 6 7 8 910 11 0 1 2 3 4 5 6 7 8 910 11 0 1 2 3 4 5 6 7 8 910 11 0 1 2 3 4 5 6 7 8 910 11 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
SP code
CR code
Red colour Blue colour
(background) black colour (background) green colour
MED228
Fig.32 SP and CR codes in Mode 1: North-west shadowing mode (transparent pattern).
1995 Jun 15
41
Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
PCA84C646; PCA84C846
handbook, full pagewidth
0 1 2 3 4 5 6 7 8 910 11 0 1 2 3 4 5 6 7 8 910 11 0 1 2 3 4 5 6 7 8 910 11 0 1 2 3 4 5 6 7 8 910 11 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
SP code
CR code
Red colour Blue colour
(background) yellow colour (background) cyan colour
MED229
SP code is a transparent pattern with the background colour of the character it intends to change or keep. CR code is always a transparent pattern with the video signal as its background. SP code can change the background colour of itself and the character/word next to it (in this example: from cyan to yellow).
Fig.33 SP and CR codes in Mode 2: Box shadowing mode.
1995 Jun 15
42
Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
PCA84C646; PCA84C846
handbook, full pagewidth
0 1 2 3 4 5 6 7 8 910 11 0 1 2 3 4 5 6 7 8 910 11 0 1 2 3 4 5 6 7 8 910 11 0 1 2 3 4 5 6 7 8 910 11 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
SP code
CR code
Red colour Blue colour
(background) yellow colour
MED230
SP and CR codes are all transparent pattern with the background colour as its colour.
Fig.34 SP and CR codes in Mode 3: Frame shadowing mode.
1995 Jun 15
43
age = 296 mm (Datasheet)
1995 Jun 15
Philips Semiconductors
Microcontrollers for TV tuning control and OSD applications
SP code
CR code
SP code
CR code
SP code
CR code
44
MED231
Character ON
Character OFF
Character ON
Red colour
Blue colour
PCA84C646; PCA84C846
Preliminary specification
Fig.35 SP and CR codes in Mode 0: No background mode (superimpose; transparent pattern) with blinking of character is set to active.
27 mm
/1 page = 296 mm (Datasheet)
1995 Jun 15
Philips Semiconductors
Microcontrollers for TV tuning control and OSD applications
SP code SP code CR code SP code
CR code
CR code
45
Character OFF Character ON
MED232
Character ON
Red colour Blue colour (background) green colour
(background) black colour
PCA84C646; PCA84C846
Preliminary specification
Fig.36 SP and CR codes in Mode 1: North-west shadowing mode (transparent pattern) with blinking of character is set to active.
27 mm
e = 296 mm (Datasheet)
1995 Jun 15
Philips Semiconductors
Microcontrollers for TV tuning control and OSD applications
SP code
CR code
SP code
CR code
SP code
CR code
46
Character OFF Character ON
MED234
Character ON
Red colour Blue colour (background) cyan colour
(background) yellow colour
PCA84C646; PCA84C846
Preliminary specification
Fig.37 SP and CR codes in Mode 2: Box shadowing mode with blinking of character set to active.
27 mm
1995 Jun 15
1/1 page = 296 mm (Datasheet)
Philips Semiconductors
Microcontrollers for TV tuning control and OSD applications
SP code
CR code
SP code
CR code
SP code
CR code
47
MED235
Character ON
Character OFF
Character ON
Red colour Blue colour
(background) yellow colour
PCA84C646; PCA84C846
Preliminary specification
Fig.38 SP and CR codes in Mode 3: Frame shadowing mode with blinking of character set to active.
27 mm
handbook, full pagewidth
1995 Jun 15
8 0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 9 10 11 0 1 2 3 4 5 6 7 8 9 10 11
Philips Semiconductors
01234
567
Microcontrollers for TV tuning control and OSD applications
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
48
MED236 - 1
In this example: - 1st character is in blinking mode - 2nd character is not - the first character bit pattern is designed such that the north-west shadow of the 1st character falls into the cell of 2nd character. When the 1st character is blinking and displayed on the screen there is no problem. However, when the 1st character is off then the shadow of the 1st character falls into 2nd character cell and will remain there. To avoid this happening: - design bit pattern in such a way that shadow does not cross the cell boundary - make adjacent characters all blinking or all not blinking.
PCA84C646; PCA84C846
Preliminary specification
Fig.39 Blinking of character is within the character cell only (12 x 18).
Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
12.5 Derivative Register 35 (VPOS)
PCA84C646; PCA84C846
Derivative Register 35 selects the vertical starting position of the display row. Table 33 Derivative Register 35 (address 35H) 7 - 6 - 5 V5 4 V4 3 V3 2 V2 1 V1 0 V0
Table 34 Description of Derivative Register 35 bits BIT 7 to 6 5 4 3 2 1 0 12.6 SYMBOL - V5 V4 V3 V2 V1 V0 Reserved. These 6 bits enable 1 of 64 vertical start positions to be selected for the display row. The vertical starting position is calculated as follows: VP = [ 4 x ( V5 to V0 ) ] x horizontal scan lines Where (V5 to V0) is the decimal value of the contents of Register 35; (V5 to V0) 0. DESCRIPTION
Derivative Register 36 (HPOS)
Derivative Register 36 selects the horizontal starting position of the display row. Table 35 Derivative Register 36 (address 36H) 7 - 6 - 5 H5 4 H4 3 H3 2 H2 1 H1 0 H0
Table 36 Description of Derivative Register 36 bits BIT 7 to 6 5 4 3 2 1 0 SYMBOL - H5 H4 H3 H2 H1 H0 Reserved. These 6 bits enable 1 of 64 horizontal start positions to be selected for the display row. The horizontal starting position is calculated as follows: HP = [ 4 x ( H5 to H0 ) + 5 ] x OSD clock cycle Where (H5 to H0) is the decimal value of the contents of Register 36; (H5 to H0) 10. DESCRIPTION
1995 Jun 15
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Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
12.7 Derivative Register 37 (BCC)
PCA84C646; PCA84C846
Derivative Register 37 selects the background colour when the OSD is in Frame shadowing mode. Table 37 Derivative Register 37 7 - 6 - 5 - 4 - 3 - 2 BCR 1 BCG 0 BCB
Table 38 Description of Derivative Register 37 bits BIT 7 to 3 2 1 0 SYMBOL - BCR BCG BCB Reserved. These three bits are used to select the background colour in Frame shadowing mode; see Table 39. DESCRIPTION
Table 39 Selection of Background colour in Frame shadowing mode BCR (RED) 0 0 0 0 1 1 1 1 BCG (GREEN) 0 0 1 1 0 0 1 1 BCB (BLUE) 0 1 0 1 0 1 0 1 black blue green cyan red magenta yellow white COLOUR
1995 Jun 15
50
Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
13 COMBINATION OF TWO OR MORE FONT CELLS TO FORM A NEW FONT The user can combine two (or more) font cells to form a new higher resolution pattern; see Figs 40, 41, 42 and 43. Combination of two cells in horizontal direction needs no special care. All 4 background/shadowing modes are applicable; see Figs 40 and 41. However the combination of two cells in a vertical direction needs the following special care: * Space between two rows should be programmed as `0' (bit <1-0> of Carriage Return Code = 00). * Row 0 in the character ROM is to be used in the North-west shadowing mode. If this mode is intended for use by this formed character font, the ROW 0 should contain the bit pattern of Row 18 of the font above it (see Figs 42 and 43).
PCA84C646; PCA84C846
0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
1
2
3
4
5
6
7
8
9
10
11 0
1
2
3
4
5
6
7
8
9
10
11 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
MRA849
Fig.40 Combination of two character cells in horizontal direction to form a new font; without shadowing.
1995 Jun 15
51
Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
PCA84C646; PCA84C846
0
handbook, full pagewidth
1
2
3
4
5
6
7
8
9
10
11 0
1
2
3
4
5
6
7
8
9
10
11 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
MRA850
Fig.41 Combination of two character cells in horizontal direction to form a new font; with North-west shadowing.
1995 Jun 15
52
Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
PCA84C646; PCA84C846
0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
(1)
0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 0 1 2 3 4 5 6 7 8 9 10 11
Cell boundary
(2)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 0 1 2 3 4 5 6 7 8 9 10 11 Character pattern stored in the ROM/RAM
MED224
Character pattern displayed on the screen
(1) The bit pattern of Row 18 of the upper character is not equal to that of Row 0 of the lower character. (2) Due to the situation of (1), in the North-west shadowing mode a gap in the shadow might occur.
Fig.42 Combination of two characters in vertical direction to form a new pattern; contents Row 18 (upper cell) not equal to contents of Row 1(lower cell).
1995 Jun 15
53
Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
PCA84C646; PCA84C846
0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
(1)
0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 0 1 2 3 4 5 6 7 8 9 10 11
Cell boundary
(2)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 0 1 2 3 4 5 6 7 8 9 10 11 Character pattern stored in the ROM/RAM
MED225
Character pattern displayed on the screen
(1) The bit pattern of Row 18 of the upper character is equal to that of Row 0 of the lower character. (2) Due to the situation of (1), in the North-west shadowing mode a gap in the shadow is avoided.
Fig.43 Combination of two characters in vertical direction to formulate a new pattern; contents Row 18 (upper cell) equal to contents of Row 1(lower cell).
1995 Jun 15
54
Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
14 OSD CLOCK IN DIFFERENT TV STANDARDS 14.1 Maximum number of characters per row 14.2
PCA84C646; PCA84C846
Maximum number of rows per frame
The number of characters per row is a function of the OSD clock frequency and the TV standard used. The active video signal period of a horizontal line is 53.5 s (see Fig.44). However, in order to reduce the jittering of the screen edge, overscan is normally applied by the TV manufacturer and this reduces the visible video signal period to 910 x 53.5 s = 48.15 s. The examples given below show how the number of characters per row and the character width may be obtained for the NTSC 525LPF/60 Hz TV standard using different OSD clock frequencies. 14.1.1 EXAMPLE 1
The number of rows per frame is a function of the number of active lines per display field and the number of vertical dots in the character matrix (which is 18). The number of rows per frame (N) is calculated as shown below. number of active lines per field N = -------------------------------------------------------------------------------18 The three examples shown below illustrate how the maximum number of rows per frame is obtained for each TV scanning standard. 14.2.1 EXAMPLE 1; NTSC 525LPF/60 HZ
* For the OSD clock frequency fOSD = 6 MHz; clock period = 0.166 s. The number of visible dots on one horizontal line is 290 (48.15 s/0.166 s). * Start of the first character dot is roughly 45 dots after HSYNC (see Section 9.2; command B, C, D). Therefore 290 - 45 = 245 dots are visible. * Since each character is composed of 12 x 18 dots, the maximum characters displayed on a row is 20 (245/12). * On a 19" TV screen, the width of a horizontal line is approximately 370 mm and this gives a character width of 18.5 mm (370 mm/20). 14.1.2 EXAMPLE 2
The number of active lines per field for this standard is between 241.5 and 249.5H (see Fig.45). If the value of 241 is used then the maximum number of rows per frame is 13. 14.2.2 EXAMPLE 2; PAL 625LPF/50 HZ
With this standard it is not necessary to divide HSYNC by two as both the horizontal and vertical frequency are doubled. The maximum number of rows per frame is 15.
* For the OSD clock frequency fOSD = 10 MHz; clock period = 0.1 s. The number of visible dots on one horizontal line is 481 (48.15 s/0.1 s). * Start of the first character dot is roughly 45 dots after HSYNC (see Section 9.2; command B, C, D). Therefore 481 - 45 = 436 dots are visible. * Since each character is composed of 12 x 18 dots, the maximum characters displayed on a row is 36 (436/12). * On a 19" TV screen, the width of a horizontal line is approximately 370 mm and this gives a character width of 10.3 mm (370 mm/36).
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55
handbook, full pagewidth
1995 Jun 15
Philips Semiconductors
blacker than black, 100%
blanking level 75%
Microcontrollers for TV tuning control and OSD applications
black, 67.5 2.5%
composite video signal
white, 12.5 2.5% 0 retrace begins blanking begins trace
56
retrace blanking ends retrace ends
RIGHT
horizontal deflection sawtooth
0
LEFT
MRA862
PCA84C646; PCA84C846
Preliminary specification
Fig.44 Composite video signal for three horizontal lines compared to three horizontal deflection sawteeth (NTSC 525LPF/60 Hz).
PCA84C646; PCA84C846
Preliminary specification
Fig.45 Vertical sync and blanking pulse intervals for one frame (NTSC 525LPF/60 Hz).
handbook, full pagewidth
1995 Jun 15
equalizing pulse interval 0.5 H 100% (75 3H (12.5 0% 0.03 V 0 start of next field 2.5)% 2.5)% H 0.5 H H
Philips Semiconductors
equalizing pulse interval
vertical sync pulse interval
blacker than black
H
H
H
black level
white level
3H
3H
zero carrier
vertical blanking 0.05 V
picture
Microcontrollers for TV tuning control and OSD applications
horizontal blanking second field, 262.5 H 16.666 s or 1/60 s
bottom of picture
first field, 262.5 H 16.666 s or 1/60 s
RIGHT
horizontal deflection sawtooth
57
active lines 241.5 to 249.5 H second field vertical deflection sawtooth trace retrace 500 to 750 s blanking ends
LEFT vertical blanking period 13 to 21 H
MRA863
active lines 241.5 to 249.5 H
vertical blanking period 13 to 21 H (825.5 to 1335.5 s)
BOTTOM
vertical deflection sawtooth
trace
retrace
blanking begins
TOP
first field vertical deflection sawtooth
Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
15 T3: 8-BIT COUNTER Figure 46 shows the block diagram of the 8-bit counter. A Schmitt-trigger input pin shapes the slow slope of the input signal into a square wave. The rising edge of the signal increases the (ripple) counter by 1. The data in the counter can be read by instruction `MOV A, D24H' (Derivative Register 24). As soon as data is read, this counter is reset to zero. Overflow or Power-on-reset both reset the counter value to zero. Minimum distance between two successive pulses (rising edges) is 30 s.
PCA84C646; PCA84C846
16 I2C-BUS MASTER SLAVE TRANSCEIVER The I2C-bus master and slave transceiver is integrated. In control register CON1 (Derivative Register 22) bits SCLE and SDAE select the function of pins DP20/SDA and DP21/SCL (for selection see Table 23); SDA = I2C-bus data and SCL = clock line. Both pins are only available in port option 2 (see Fig.48).
handbook, full pagewidth
T3
CK RESET
8-BIT COUNTER READ ENABLE Q0 to Q7 Data bus
Power-on-reset READ D24
MLC075
Fig.46 T3: 8-bit counter block diagram.
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58
Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
17 DERIVATIVE REGISTERS
PCA84C646; PCA84C846
Table 40 Register map PCA84C646/PCA84C846 Values within parenthesis show the bit state after a reset operation; `X' denotes an undefined state. ADDR (HEX) 00 01 02 03 04 05 10 11 12 13 14 15 16 17 18 19 20 21 22 23 REG DP0R (Terminal) DP1R (Terminal) DP2R (Terminal) DP0R (Latch) DP1R (Latch) DP2R (Latch) PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 VSTL VSTH AFCCN PWME CON1 CON2 7 DP07 (X) - (X) - (X) DP07 (1) - (X) - (X) - (X) - (X) - (X) - (X) - (X) - (X) - (X) - (X) - (X) - (X) - (X) PWM7E (0) TDACE (0) VINT (0) 6 DP06 (X) - (X) - (X) DP06 (1) - (X) - (X) PWM06 (0) PWM16 (0) PWM26 (0) PWM36 (0) - (X) - (X) - (X) - (X) VST06 (0) VST13 (0) AFCH1 (0) PWM6E (0) SCLE (0) VIEN (0) 5 DP05 (X) - (X) - (X) DP05 (1) - (X) - (X) PWM05 (0) PWM15 (0) PWM25 (0) PWM35 (0) PWM45 (0) PWM55 (0) PWM65 (0) PWM75 (0) VST05 (0) VST12 (0) AFCH0 (0) PWM5E (0) SDAE (0) - (X) 4 DP04 (X) - (X) - (X) DP04 (1) - (X) - (X) PWM04 (0) PWM14 (0) PWM24 (0) PWM34 (0) PWM44 (0) PWM54 (0) PWM64 (0) PWM74 (0) VST04 (0) VST11 (0) AFCV3 (0) PWM4E (0) AFCE2 (0) - (X) 3 DP03 (X) DP13 (X) DP23 (X) DP03 (1) DP13 (1) DP23 (1) PWM03 (0) PWM13 (0) PWM23 (0) PWM33 (0) PWM43 (0) PWM53 (0) PWM63 (0) PWM73 (0) VST03 (0) VST10 (0) AFCV2 (0) PWM3E (0) AFCE1 (0) - (X) 2 DP02 (X) DP12 (X) DP22 (X) DP02 (1) DP12 (1) DP22 (1) PWM02 (0) PWM12 (0) PWM22 (0) PWM32 (0) PWM42 (0) PWM52 (0) PWM62 (0) PWM72 (0) VST02 (0) VST09 (0) AFCV1 (0) PWM2E (0) AFCE0 (0) P14LVL (0) 1 DP01 (X) DP11 (X) DP21 (X) DP01 (1) DP11 (1) DP21 (1) PWM01 (0) PWM11 (0) PWM21 (0) PWM31 (0) PWM41 (0) PWM51 (0) PWM61 (0) PWM71 (0) VST01 (0) VST08 (0) AFCV0 (0) PWM1E (0) VOW1E (0) P7LVL (0) 0 DP00 (X) DP10 (X) DP20 (X) DP00 (1) DP10 (1) DP20 (1) PWM00 (0) PWM10 (0) PWM20 (0) PWM30 (0) PWM40 (0) PWM50 (0) PWM60 (0) PWM70 (0) VST00 (0) VST07 (0) AFCC(1) (X) PWM0E (0) VOW0E (0) P6LVL (0) R/W R R R RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
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59
Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
ADDR (HEX) 24 25 30 31 32 33 34 35 36 37 Note 1. This bit is Read only. REG T3CON PLLCN DCRAR DCRTR DCRCR CON3 CON4 VPOS HPOS BCC 7 T3B7 (0) - (X) - (X) - (X) - (X) - (X) - (X) - (X) - (X) - (X) 6 T3B6 (0) PLL6 (0) - (X) - (X) - (X) - (X) - (X) - (X) - (X) - (X) 5 T3B5 (0) PLL5 (0) DCRA5 (0) - (X) DCRC5 (1) - (X) S1 (0) V5 (1) H5 (0) - (X) 4 T3B4 (0) PLL4 (0) DCRA4 (0) - (X) DCRC4 (1) - (X) S0 (0) V4 (1) H4 (0) - (X) 3 T3B3 (0) PLL3 (0) DCRA3 (0) DCRT3 (1) DCRC3 (1) BR1 (0) Hp (0) V3 (1) H3 (0) - (X)
PCA84C646; PCA84C846
2 T3B2 (0) PLL2 (0) DCRA2 (0) DCRT2 (1) DCRC2 (1) BR0 (0) Vp (0) V2 (1) H2 (0) BCR (0)
1 T3B1 (0) PLL1 (0) DCRA1 (0) DCRT1 (1) DCRC1 (1) BF1 (1) Bp (1) V1 (1) H1 (0) BCG (0)
0 T3B0 (0) PLL0 (0) DCRA0 (0) DCRT0 (1) DCRC0 (1) BF0 (1) EN (0) V0 (1) H0 (0) BCB (1)
R/W R RW RW W W RW RW W W W
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60
Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
18 INPUT/OUTPUT There are 3 different port options available for the port pins in the 84CXXX derivatives (see Figs 47, 48 and 49). Each I/O port line may be individually configured using one of three mask options. The three I/O mask options are specified below: Option 1 Standard input/output with switched pull-up current source; this is shown in Fig.47. Option 1 Input/output with Open drain output; this is shown in Fig.48. Option 2 Push-pull output; this is shown in Fig.49. The state of each output port after a Power-on-reset can also be selected using the mask options. All port mask options are given in Section 19.1.
PCA84C646; PCA84C846
The output stage consists of 4 transistors: TR1: N - channel transistor for `sink' TR2: P - channel transistor for `boost-up' TR3: P - channel transistor for `pull-up' TR4: P - channel transistor for `constant current'. See Tables 41 and 42 for possible port option list.
handbook, full pagewidth
write pulse OUTL/ORL/ANL/MOV
data bus
VDD TR2 100 A typical (VO = 0.7 VDD ) TR3
D MQ Master
D SQ Slave SQ
TR1
I/O port line
VSS ORL/ANL/MOV
MED186 - 1
IN/MOV
Fig.47 Standard output with switched pull-up current source (Option 1).
1995 Jun 15
61
Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
PCA84C646; PCA84C846
handbook, full pagewidth
write pulse OUTL/ORL/ANL data bus
V DD
D MQ Master
D SQ Slave TR1
I/O port line
VSS ORL/ANL IN
MED187 - 1
Fig.48 Open drain output (Option 2).
handbook, full pagewidth
VDD write pulse OUTL/ORL/ANL
data bus
TR2
D MQ Master
D SQ Slave TR1
I/O port line
VSS ORL/ANL
MED188
IN
Fig.49 Push-pull output (Option 3).
1995 Jun 15
62
Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
19 OPTION LISTS 19.1 Port option
PCA84C646; PCA84C846
For the port options (1, 2 and 3) see Figs 47, 48 and 49. Table 41 Port options for making piggyback Only the port pins whose options are left blank, e.g. DP00, can be user mask programmable. PORT P00 P01 P02 P03 P04 P05 P06 P07 Notes 1. S = SET (and R = RESET), initial H or L after power-on reset. 2. Option 2 or 3 only (i.e. output only). Table 42 Port options for production Only the port pins whose options are left blank, e.g. DP00, can be user mask programmable. PORT P00 P01 P02 P03 P04 P05 P06 P07 Notes 1. S = SET (and R = RESET), initial H or L after power-on reset. 2. Option 2 or 3 only (i.e. output only). 19.2 On-chip oscillator transconductance OPTION LOW (gmL) MEDIUM (gmM) HIGH (gmH) typ. gm at 5 V 0.4 mS 1.6 mS 4.5 mS fosc FOR QUARTZ 1 to 6 MHz 4 to 10 MHz not allowed fosc FOR PXE not allowed 1 to 6 MHz 3 to 10 MHz PIN 13 14 15 16 17 18 19 20 OPTION PORT/DPORT P10 P11 P12 P14 DP10 DP11 DP12 DP13 PIN 7 8 10 12 38 37 36 9 OPTION DPORT DP00 DP01 DP02 DP03 DP04 DP05 DP06 DP07 PIN 29 28 27 26 25 24 23 22 VOB(2) VOW2(2) 1 2 OPTION DPORT DP20 DP21 DP22 DP23 PIN 40 39 3 4 OPTION 2 2 S(1) S PIN 13 14 15 16 17 18 19 20 OPTION PORT/DPORT 1 1 1 1 1 1 1 1 S(1) S S S S S S S P10 P11 P12 P14 DP10 DP11 DP12 DP13 PIN 7 8 10 12 38 37 36 9 OPTION 1 1 1 1 S S S S DPORT DP00 DP01 DP02 DP03 DP04 DP05 DP06 DP07 PIN 29 28 27 26 25 24 23 22 VOB(2) VOW2(2) 1 2 OPTION DPORT DP20 DP21 DP22 DP23 PIN 40 39 3 4 OPTION 2 2 S S
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Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
20 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134) SYMBOL VDD VI Ptot IOH IOL Tstg Tamb supply voltage all input voltages total power dissipation maximum source current for all port lines maximum sink current for all port lines storage temperature ambient operating temperature PARAMETER
PCA84C646; PCA84C846
MIN. -0.3 -0.3 - - - -55 -20
MAX. +7 1 -10 30 +125 +70 V W VDD + 0.3 V
UNIT
mA mA C C
21 DC CHARACTERISTICS VDD = 5 V; VSS = 0 V; Tamb = -20 to +70 C; all voltages with respect to VSS; unless otherwise specified. SYMBOL VDD IDD PARAMETER operating supply voltage operating supply current fOSD(RC), fOSD(LC) = fxtal fxtal = 10 MHz fxtal = 6 MHz fOSD(RC), fOSD(LC) = stop fxtal = 10 MHz fxtal = 6 MHz Input Ports P00, P01, DP00, DP01 and DP02 VIL VIH ILI LOW level input voltage HIGH level input voltage input leakage current VDD = 4.5 V to 5.5 V VDD = 4.5 V to 5.5 V VDD = 4.5 V to 5.5 V; VSS < VI < VDD IOL = 10 mA VO = 0.7VDD VO = VSS 0 - - - 0.3VDD V VDD 10 V A 0.7VDD - - - 3 1.5 6 4 mA mA - - 5 3.5 10 7 mA mA CONDITIONS MIN. 4.5 TYP. 5.0 MAX. 5.5 UNIT V
Output Port P00 VOL IOH LOW level output voltage HIGH level pull-up output source current HIGH level pull-up output source current DP00/PWM00 to DP07/PWM07 as derivative Port IOL IOH LOW level output sink current HIGH level pull-up output source current HIGH level pull-up output source current VOL = 0.4 V VO = 0.7VDD VO = VSS 5.0 -40 - -3.0 12.0 -100 -140 -7.0 - - -400 - mA A A mA - -40 - -3.0 - -100 -140 -7.0 1.2 - -400 - V A A mA
HIGH level push-pull output source current VO = VDD - 0.4 V
HIGH level push-pull output source current VO = VDD - 0.4 V
1995 Jun 15
64
Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
SYMBOL PARAMETER
PCA84C646; PCA84C846
CONDITIONS
MIN.
TYP.
MAX. - - -400 - - - -400 - - - -400 - - - -400 - - - -400 - - - -400 - - - -400 -
UNIT
DP00/PWM00 to DP07/PWM07 as PWM output Port IOL IOH LOW level output sink current HIGH level pull-up output source current HIGH level pull-up output source current Port P10 to P13 outputs IOL IOH LOW level output sink current HIGH level pull-up output source current HIGH level pull-up output source current Outputs VOB and VOW2 IOL IOH LOW level output sink current HIGH level pull-up output source current HIGH level pull-up output source current VOL = 0.4 V VO = 0.7VDD VO = VSS 1.4 -40 - -1.4 3.0 -100 -140 -3 mA A A mA VOL = 0.4 V VO = 0.7VDD VO = VSS 5.0 -40 - -3.0 12.0 -100 -140 -7.0 mA A A mA VOL = 0.4 V VO = 0.7VDD VO = VSS 0.7 -40 - -0.7 1.5 -100 -140 -1.5 mA A A mA
HIGH level push-pull output source current VO = VDD - 0.4 V
HIGH level push-pull output source current VO = VDD - 0.4 V
HIGH level push-pull output source current VO = VDD - 0.4 V DP10/AFC0, DP11/AFC1 and DP12/AFC2 as derivative output Port IOL IOH LOW level output sink current HIGH level pull-up output source current HIGH level pull-up output source current DP20/SDA and DP21/SCL outputs IOL IOH LOW level output sink current HIGH level pull-up output source current HIGH level pull-up output source current VOL = 0.4 V VO = 0.7VDD VO = VSS VOL = 0.4 V VO = 0.7VDD VO = VSS
5.0 -40 - -3.0
12.0 -100 -140 -7.0 - -100 -140 -7.0
mA A A mA
HIGH level push-pull output source current VO = VDD - 0.4 V
3.0 -40 - -
mA A A mA
HIGH level push-pull output source current VO = VDD - 0.4 V DP22/VOW1, DP23/VOW0 and DP13/TDAC as derivative output Port IOL IOH LOW level output sink current HIGH level pull-up output source current HIGH level pull-up output source current DP22/VOW1 and DP23/VOW0 as VOWi output IOL IOH LOW level output sink current HIGH level pull-up output source current HIGH level pull-up output source current VOL = 0.4 V VO = 0.7VDD VO = VSS VOL = 0.4 V VO = 0.7VDD VO = VSS
5.0 -40 - -3.0
12.0 -100 -140 -7.0
mA A A mA
HIGH level push-pull output source current VO = VDD - 0.4 V
1.4 -40 - -1.4
3.0 -100 -140 -3.0
mA A A mA
HIGH level push-pull output source current VO = VDD - 0.4 V
1995 Jun 15
65
Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
SYMBOL PARAMETER
PCA84C646; PCA84C846
CONDITIONS
MIN.
TYP.
MAX. - - -400 -
UNIT
DP13/TDAC as TDAC output IOL IOH LOW level output sink current HIGH level pull-up output source current HIGH level pull-up output source current VOL = 0.4 V VO = 0.7VDD VO = VSS 1.4 -40 - -1.4 3.0 -100 -140 -3.0 - - mA A A mA
HIGH level push-pull output source current VO = VDD - 0.4 V EMU/TEST, RESET, INT/T0, T1, HSYNC, VSYNC and T3 (Schmitt-trigger input) VIL VIH ILI LOW level input voltage HIGH level input voltage input leakage current VDD = 4.5 V to 5.5 V VDD = 4.5 V to 5.5 V VDD = 4.5 V to 5.5 V; VSS < VI < VDD
0 -1.0
0.3VDD V VDD +1.0 V A
0.7VDD -
22 AC CHARACTERISTICS VDD = 5 V; Tamb = -20 to +70 C; all voltages with respect to VSS; unless otherwise specified. SYMBOL Oscillator fxtal fosc-XTAL fosc-PXE fosc-XTAL fosc-PXE fosc-XTAL fosc-PXE CXTAL1 crystal frequency (note 1) oscillator frequency; option 1 oscillator frequency; option 2 oscillator frequency; option 3 external capacitance at XTAL1 with XTAL resonator with PXE resonator CXTAL2 external capacitance at XTAL2 with XTAL resonator with PXE resonator fOSD Note 1. Oscillator with three (3) options for optimum use. 23 AFC CHARACTERISTICS SYMBOL TAFC PARAMETER conversion time (from any change in the AFC: channel number, voltage level, enable/disable) with fxtal = 10 MHz comparator analog input voltage conversion error range 66 MIN. - TYP. - MAX. 7 UNIT s OSD clock frequency - 4.0 not required 30 8.0 100 12.0 pF pF MHz - not required 30 100 pF pF gm = 0.4 mS (typ.) gm = 1.6 mS (typ.) gm = 4.5 mS (typ.) 1 1 4.0 1.0 3.0 - - - - - 10.0 6.0 10.0 6.0 10.0 MHz MHz MHz MHz MHz MHz MHz PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
not allowed
not allowed
DP10/AFC0, DP11/AFC1 and DP12/AFC2 comparator input VAI VAE 1995 Jun 15 VSS - - - VDD 0.5 V LSB
Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
24 PACKAGE OUTLINE SDIP42: plastic shrink dual in-line package; 42 leads (600 mil)
PCA84C646; PCA84C846
SOT270-1
seating plane
D
ME
A2
A
L
A1 c Z e b1 wM (e 1) MH b 42 22
pin 1 index E
1
21
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 5.08 A1 min. 0.51 A2 max. 4.0 b 1.3 0.8 b1 0.53 0.40 c 0.32 0.23 D (1) 38.9 38.4 E (1) 14.0 13.7 e 1.778 e1 15.24 L 3.2 2.9 ME 15.80 15.24 MH 17.15 15.90 w 0.18 Z (1) max. 1.73
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT270-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 90-02-13 95-02-04
1995 Jun 15
67
Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
25 SOLDERING 25.1 Introduction
PCA84C646; PCA84C846
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 25.2 Soldering by dipping or by wave
The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified storage maximum (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 25.3 Repairing soldered joints
Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds.
1995 Jun 15
68
Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
26 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
PCA84C646; PCA84C846
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 27 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 28 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1995 Jun 15
69
Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
NOTES
PCA84C646; PCA84C846
1995 Jun 15
70
Philips Semiconductors
Preliminary specification
Microcontrollers for TV tuning control and OSD applications
NOTES
PCA84C646; PCA84C846
1995 Jun 15
71
Philips Semiconductors - a worldwide company
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Internet: http://www.semiconductors.philips.com/ps/ For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-724825 SCD40 (c) Philips Electronics N.V. 1995
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
453061/1500/03/pp72 Document order number: Date of release: 1995 Jun 15 9397 750 00166

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